India Notifies ₹1.27 Lakh Crore Semicon 2.0 Scheme to Boost Semiconductor Ecosystem

Key Facts

• The Government of India notified the Semicon 2.0 scheme on 31 August 2026, with a total fiscal outlay of ₹1,27,500 crore.
• The scheme is structured around six strategic pillars: design, machines and materials, semiconductor fabrication units, advanced packaging/assembly/testing (ATMP/OSAT), research and development, and talent development.
• Silicon wafer fabs with a minimum investment of ₹20,000 crore are eligible for 40% fiscal support on capital expenditure on a pari-passu basis.
• Compound semiconductor, display, and other specialized fabs are eligible for 35% fiscal support.
• The scheme includes design-linked incentives for startups and Indian or Overseas Citizen of India (OCI)-owned companies, with deployment-linked incentives fixed at 9% of net sales for up to five years, capped at ₹30 crore per application.
• An ambitious target has been set to train 100,000 additional semiconductor engineers, building on 85,000 engineers trained earlier under previous initiatives.
• A high-level expert panel will be established to identify strategic semiconductor chips of national interest; this panel will be co-chaired by the Principal Scientific Adviser and the National Security Adviser.
• The government expects the scheme to attract about ₹4 lakh crore in investments and generate production worth ₹2 lakh crore in the domestic semiconductor ecosystem.

Background & Context

The Semicon India Programme was initially launched to develop a robust semiconductor and display ecosystem in India. Following the success of Semicon 1.0, the government launched Semicon 2.0 to expand the scope and enhance support across the entire semiconductor value chain. Semiconductors are critical for India's digital infrastructure, telecommunications, defense, and economic growth. Given the global semiconductor supply chain vulnerabilities exposed in recent years, India is aiming for self-reliance and strengthening its domestic manufacturing and innovation ecosystem.

Semicon 2.0 shifts the focus from only chip manufacturing to building a comprehensive ecosystem that includes advanced packaging (ATMP/OSAT), R&D, and talent development, thereby fostering a full-stack semiconductor industry in India.

Why This Matters for Exams

The Semicon 2.0 scheme is an important government initiative indicative of India's push towards technological self-reliance and strategic autonomy in critical sectors. It is a relevant topic in government schemes, industrial development, and technology-related questions in competitive exams such as UPSC, SSC, banking, and state public service commission exams.

Questions may cover scheme objectives, fiscal incentives, strategic importance, and talent development targets, hence understanding this scheme helps in preparing for current affairs and policy-based questions.

Points to Remember

• Semicon 2.0 was notified on 31 August 2026 with a budgetary outlay of ₹1,27,500 crore.
• Six strategic pillars: design, machines and materials, fabs, ATMP/OSAT, research & development, and talent development.
• 40% fiscal support provided for silicon wafer fabs investing ₹20,000 crore or more, 35% for compound/display fabs.
• Design-linked incentives available to startups and OCI-owned companies, with deployment-linked incentives at 9% of net sales, capped at ₹30 crore.
• Target to train 100,000 new semiconductor engineers to build skilled talent required for the sector's growth.
• High-level expert panel co-chaired by the Principal Scientific Adviser and National Security Adviser to guide incentives for strategic chips.
• Expected attraction of ₹4 lakh crore investment and production output of ₹2 lakh crore from the semiconductor ecosystem.

Practice MCQs

Question 1

1. ₹76,000 crore
2. ₹1,27,500 crore
3. ₹2,00,000 crore
4. ₹50,000 crore

Answer: 2 ₹1,27,500 crore is the fiscal outlay of the Semicon 2.0 scheme notified in 2026.

Question 2

1. 20,000 engineers
2. 85,000 engineers
3. 100,000 engineers
4. 150,000 engineers

Answer: 3 Semicon 2.0 aims to train an additional 100,000 semiconductor engineers.

Question 3

1. Principal Scientific Adviser and Finance Minister
2. National Security Adviser and Defence Minister
3. Principal Scientific Adviser and National Security Adviser
4. Electronics Minister and Prime Minister

Answer: 3 The high-level expert panel is co-chaired by the Principal Scientific Adviser and the National Security Adviser.